The PCMCIA specification was created to standardize a removable peripheral device for personal computers. The PCMCIA specification describes the features required for PCMCIA devices. These features include physical dimensions and electrical specifications. The PCMCIA electrical specification can further be divided into two card categories, input/output cards and memory cards. This invention is described by the memory card category of the PCMCIA specification.
Although the memory specification is intended to describe PCMCIA devices using general memory technology, the specification tends to limit memory selection to either SRAM or FLASH technology. The specification is not well suited to other types of memory, particularly DRAM. Signals and functions unique to DRAM technology, such as refresh, are not readily addressed by the PCMCIA specification.
The purpose of this invention is to allow the use of DRAM technology in a PCMCIA device. This will allow the user to take advantage of DRAM technology's inherent benefits. These include higher density, lower cost, and improved data integrity.
This invention not only allows DRAM to function in a PCMCIA device, but it also handles any peculiarities of DRAM technology. To the user, the invention will appear as an SRAM device.
The invention must perform several functions in order to replace a PCMCIA SRAM based memory card. It must manage the power obtained from its host system and properly regulate it to the DRAM. It must communicate through PCMCIA signals and translate SRAM protocols to DRAM protocols. At the same time, the invention must refresh the DRAM and handle any refresh/PCMCIA access contention. When the invention is removed from its host computer system, the invention must detect the removal, force the DRAM into its data retention mode, modify the DRAM voltages to facilitate the data retention mode, and switch the source of the power supply from the host computer system to an alternate supply i.e. battery. When the invention is returned to a host, it must switch its power source from the alternate supply to the host, adjust the DRAM voltage to its operating voltage, and force the DRAM out of data-retention mode into an active mode. All of these functions will be independent of any user intervention.
Previous inventions have addressed the problem of configuring a DRAM device to function as an SRAM device. Each of these inventions have failed to address the further inventive steps associated with providing the associated power management as well as the control of the DRAM operations including data retention operations required for use of a DRAM component on a PCMCIA card. For example, U.S. Pat. No. 5,276,843, issued Jan. 4, 1994 to Tillinghast et al., discusses the concept of configuring a DRAM to appear to function: as a SRAM. This patent fails to address the problems inherent in operating a DRAM in a PCMCIA SRAM environment. The present invention provides complex power management functions as well as data retention operation of the DRAM which permit the DRAM to function on a PCMCIA card. These problems are not addressed by this patent. Furthermore, U.S. Pat. No. 4,958,322, issued Sep. 18, 1990 to Kosugi et al., describes a module containing DRAMs which is configured to appear as an SRAM module through the use of external logic. This patent does not address any of the problems inherent in a PCMCIA based DRAM invention. Additionally, the patent requires the use of external signals for refreshing the DRAM, these signals would not be available to the DRAM in a PCMCIA implementation.
Other inventions have addressed the concept of power loss detection, however, these inventions have failed to solve the particular problems encountered in providing such detection as a step in the overall power management of a DRAM in a PCMCIA based implementation. For example, U.S. Pat. No. 5,365,221, issued Nov. 15, 1994 to Fennell et al., teaches a low battery detection circuit coupled with an annunciator which generates a sensible audible alert. U.S. Pat. No. 5,072,103, issued Dec. 10, 1991 to Nara et al., teaches a low battery voltage detection device which strives to reduce its own power consumption so as to prolong battery life. U.S. Pat. No. 5,262,868, issued Nov. 16, 1993 to Kaneko et al., consists of a load dependent low battery voltage detection circuit and an alarm notifier. None of these inventions address the problems inherent in managing power to a DRAM in a PCMCIA implementation. In particular, these inventions do not solve the problems inherent in providing sufficient time after a voltage loss is detected so as to allow the associated circuitry to compensate for the loss ensuring the data integrity of the DRAM device.